0 Preface
With the continuous progress of science and technology, the application of smart cards has become more and more extensive, involving various fields of human life, such as business, medical, insurance, transportation, social and other public utilities, so how to design an efficient and stable smart card The operating system port has a high social significance. Here, the operating system communication and other modules of the hardware are designed for the hardware structure of the smart card, and a test scheme is proposed to detect the stability of the underlying module of the chip.
1 Smart Card Operating System Overview
The chip operating system (COS) is generally developed around the characteristics of the smart cards it serves. Compared with the operating system on a common microcomputer, COS is closer to the monitoring program in nature. The basic problems of the card operating system are explained here with specific development examples, and a feasible and testable chip layer design scheme and a chip bottom layer test scheme are proposed.
2 COS chip module design
The design of the COS bottom module is closely related to the internal memory partition of the smart card. The design and development are performed according to the functions specified in the international standards.
IS07816 is the international standard that the contact smart card must follow. IS07816-3 mainly describes the electrical signal and transmission protocol of the contact smart card, including the voltage and current withstand range of each contact, the actual representation of each information bit of the card reset response and T=0 T=1 transmission protocol. ISO/IEC 7816-3 specifies the electrical characteristics and transmission protocols of IC cards. Including this type of card and interface equipment asked for power, electrical signal protocol and information exchange protocol. In the communication process, the interface device provides the IC card with power (Vcc), reset signal (RST) and clock (CLK), and the card and the interface device communicate serially through the I/O port.
(1) Communication module design. According to the T=0 asynchronous half-duplex character transmission protocol, the Ic card and the interface device are transmitted in units of characters (referred to as character frames), and even parity is used, and each character is composed of 10 b. Before transmitting the character frame, the I/O line is in state z, the first b is the start bit (state A); the following 8 b is the data bits D1 to D8; the 10 b is the even parity, ie, the 8 bit data and parity The number of 1s in parity bits is even.
Serial communication is transmitted in bits. The width (duration) of each bit is defined as the Elementary Time Unit (ETU). The width of the message during the reset reply is called the "initial ETU" and it is equal to 372 clock cycles, ie 1 ETU = 372/f. The width of the information after resetting the response is called "current ETU" and its calculation formula is: Current ETU = (F/D) (1/f). Where: F is the clock frequency conversion factor; D is the bit rate adjustment factor; f is the clock frequency.
The IC card must communicate with the corresponding read-write device (IFD). From this perspective, the function of the smart IC card operating system is to receive commands, execute commands, and return the results to the read-write device (IFD) from the read-write device (IFD). Therefore, the communication management function module has a very important role in the operating system. The communication management function module mainly realizes the following functions: realizes the data link layer transmission management function of a certain communication protocol; realizes the ATR (Reset Response) and other functions specified in the ISO/IEC 7816 standard; and is a function module in the operating system. Provide the appropriate interface.
According to the ISO/IEC 7816 standard, there are many kinds of communication protocols between the IC card and the read-write device. Generally, one type of card supports only one kind of communication protocol. The following uses the intelligent IC card of the T=0 character transmission protocol conforming to the ISO/IEC 7816-3 standard as an example to introduce the communication management function (the communication management function of the card supporting other communication protocols is similar to this).
After the ICC is powered on, the IFD will send command data to the ICC. In such a typical communication process, the communication management function is mainly engaged in the six steps of the specific work. As shown in Figure 1.
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Figure 1: Specific steps for 6 steps
The following is the source code associated with the card receive instruction:
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(2) Hardware module design. After the smart card COS is powered on, it first needs to initialize the chip, and mainly sets the following aspects: the frequency at which the chip initially works, and whether it uses the FSB or IF; the rate at which the serial port of the chip is initially used (usually a baud rate of “11â€). ) - Chip serial port operation modes (including T=0 or T=1 protocol, forward or reverse transmission, odd or even parity, etc.); initial mapping of the memory.
A smart card chip (hereinafter, the 51 series smart card chip as an example) generally includes tens to hundreds of kilobytes of FLASH, and is erased in units of one page. According to the characteristics of FLASH programming, that is, 1 can be written as 0, and 0 cannot be Written as 1, so in order to ensure the correctness of writing data when designing programming writing function, we adopt the following ways to achieve this function:
The first step: take out the data to be written into the address (A), and perform the AND operation on the data to be written (B) (the result is C);
The second step: writing data at the address where data is to be written (B);
The third step is to take out the data of the address after writing the human data and compare it with the data C.
For the 51 series smart card chips, since the standard 8051 supports 64 KB maximum program memory, the chip uses BANK addressing. This often requires a mapping function to implement different BANK jumps. If the program memory of a smart card chip uses 128 KB of FLASH to store COS and user data. The 128 KB FLASH divides four 32 KB BANKs. In these four areas, the Commom area is the common area of ​​three Bnaks. That is, the Commom area and each 32 KB BANK can form a 64 KB continuous space. The three Bnaks cannot directly access each other. Instead, they must call programs in the Commom area to achieve mutual access. Therefore, when creating a project, always use programs and constants, such as interrupt entry function, Bank Switch jump table, etc., in the Commom area to achieve mutual access to each area.
(3) Abnormal protection module design. IS07816-3 specifies that the delay between the rising edges of 2 consecutive characters is at least 12 ETUs, and the delay between the rising edges of 2 consecutive characters shall not exceed 9 600 ETU. Therefore, the COS is designed to send "60" to achieve normal communication.
Send "60" using the chip timer interrupt mode, set the timer's operating mode, use the initial value of the clock and. Timer interrupt service routine implementation process: Turn off sending "60" timer; send "60"; open and send "60" timer.
The exception handling of the operating system. This function is a function that is called when the COS performs an abnormal state. When entering an abnormal state, the timer that sends "60" is turned off, and then enters an infinite loop state.
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3 chip test program design
The following presents a test scheme for chip module functions. Embedded Test COS.
(1) Testing COS test platform. T-COS platform by MAIN. C file, API. C file, constant configuration, A51 file and chip library, LIB file composition. Among them, for different chips, main. c, api. C is the same, but constant configuration files and chip library files are different and need to be changed or replaced when used.
In addition, MAIN. The CommandInterpreter() command interpreter function in the C file is an interpreted explanation of the send command (in this function, does the command have been defined for all the functions that need to be tested). The function body of the function being tested is in the API. C file. Chip library in API. C file is specifically called.
This Testing COS can be directly written to the smart card. The design idea is: Directly call the hardware module function in the form of a direct APDU instruction call, such as rubbing a page function. After executing the instruction, the function returns a status word.
The main program is an infinite loop, as follows:
The command interpreter function supports multiple functions, provides an interface for the user to directly operate the hardware, and can perform multiple operations on the chip by sending an APDU instruction.
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For example: APDU:80 00 10 00 00 indicates the page where the erase address 0x1000 is located.
APDU: 80 0C 10 00 10 indicates that data of length Oxl0 is read starting from address Oxl000.
(2) Use of the Tesling COS test platform. T-COS test platform test process, as shown in Figure 2:
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(3) Testing COS test platform limitations analysis. The T-COS platform is easy to use and easy to observe, but it cannot observe the process. Therefore, if the returned result is inconsistent with the expected result or an error occurs, the cause of the error cannot be determined. In this case, you need to use an emulator to track the execution process and ultimately find out the cause of the problem.
4 Conclusion
The fundamental part of a smart card operating system is the robustness of each module at the bottom of the chip. The development of the chip layer is one of the important components of the development of telecommunications, tax control and other products, and it is also the most basic part. In order to ensure that telecommunication and tax control products can be smoothly transplanted between different chips, certain requirements and standards need to be put forward for the development of the chip layer, which can ensure the consistency of the upper layer development.